Enhancing FD-SOI MOSFET Performance and Reliability: A Comparative Study of High-k TiO₂ versus Standard SiO₂ Buried Oxides

Abstract

The continuous downscaling of CMOS technology forces us to use material integration. Novel material integration helps us get past the limits of standard Silicon-On-Insulator (SOI) architectures. In this paper we study the performance and reliability of Depleted SOI (FD‑SOI) MOSFETs when we replace the conventional Silicon Dioxide (SiO₂) Buried Oxide (BOX) with a high‑permittivity Rutile‑phase Titanium Dioxide (TiO₂, ). We focus on Depleted SOI (FD‑SOI) MOSFETs. Through analysis and Silvaco TCAD simulations we show that the high‑k BOX significantly enhances vertical capacitive coupling. The high‑k BOX increases the saturation drain  from 1.75 mA to over 2.8 mA compared with the standard reference. The high‑k BOX does not cause a threshold voltage shift. The high permittivity lets the dielectric layer be physically thicker while the equivalent capacitance stays the same. The high permittivity also suppresses the tunneling leakage currents dramatically. The high permittivity reduces the reliability issues such as Time‑Dependent Dielectric Breakdown TDDB. Beyond electrical characterization, this study evaluates the industrial feasibility of the proposed architecture. We analyze critical manufacturing challenges, including Atomic Layer Deposition (ALD) throughput, wafer bonding defects, and thermal instability due to crystallization. Finally, a comparative economic analysis reveals that the modified TiO₂ SOI process entails production costs exceeding five times that of standard Bulk MOSFETs, currently restricting this technology to ultra-high-performance niche applications in aerospace and military sectors.